A Variable Latency Pipelined Floating-Point Adder

Addition is the most frequent oating-point operation in modern microprocessors. Due to its complex shift-add-shift-round data ow, oating-point addition can have a long latency. To achieve maximum system performance, it is necessary to design the oating-point adder to have minimum latency, while still providing maximum throughput. This paper proposes a new oating-point addition algorithm which exploits the ability of dynamicallyscheduled processors to utilize functional units which complete in variable time. By recognizing that certain operand combinations do not require all of the steps in the complex addition data ow, the average latency is reduced. Simulation on SPECfp92 applications demonstrates that a speedup in average addition latency of 1.33 can be achieved using this algorithm, while still maintaining single cycle throughput.